View TC90101FG_315369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC90101FG
Y/C separation & Video Decoder
* * * * * * *
LQFP100-P-1414-0.5C
* * * * *
TOSHIBA is continually working to improve the quality and the reliability of its product. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
TC90101FG
Clamp
Sync Sep.
Clock Gene.
reference clock
SW
ID1
SW
Y CVBS
27 10bit ADC
AGC
SW
C Cb
MPX
27M 8bit ADC
line M 4fsc
Cr
27M 8bit ADC IIC-BUS
SW
SCL SDA
TC90101FG
Power supply for X' tal OSC circuit X' tal OSC circuit input terminal X' tal OSC circuit output terminal GND for X' tal OSC circuit
Reset terminal (Low :Reset Hi :normal) terminal (5V input possible terminal (5V input possible)
TC90101FG
TC90101FG
Functional Description
4.1 General Description
TC90101FG is a Video decoder device for multi color system (525i. 625i). TC90101FG also has a through mode and sync processing for 525p & 625p component signal. 1.TC90101FG has input interface for CVBS S-Video, Y external circuit as below.
CVBS
LPF
b r. For RGB signal it needs some
SCART
G
RGB
R
YCbCr
AMP/LPF AMP/LPF AMP/LPF
Y b r
TC90101FG
CGP
2. Automatic clamp control circuit. 3. Multi 3line comb filter. 4. Multi color decoder and sync processing. 5. Color system detection circuit. (Selectable auto detection and manual setting.) Result of color system dtection can be read via IIC. 6. Frequncy detection circuit for 525i/525p/625i/625p for component signal. 7. AGC circuit circuit at after stage of ADC. 8. Picture processing circuit for CVBS, S-Video, 525i/625I component signal. 9. Selectable ITUR-601, ITUR-656 output interface. 10. VBI data slice function (525i ID-1/525p ID-1/ CCD/ WSS). It can be read via IIC. 11. Macrovision detection circuit. 12. Noise level detection circuit. 13. Superposition function for IIC read data on ITUR-656 ouitput.
1. Clock System TC90101FG has a digital VCO circuit which uses 42MHz free run X'tal OSC.
2.0 Input interface Input signal CVBS Y(S-Video & Component ) C(S-Video & Component ) Cb Cr Pin name CVBS IN YIN CIN Cb IN Cr IN Terminal 81 78 86 88 94
2.1 Selection input signal Input signal can be set via INSEL at sub address 00hex. INSEL : 00 : CVBS 01: S-Video 10: YCbCr 11: SCART( ** ) ( * ) : it's not available to input RGB signal dilectlly. It's needs RGB to YCbCr conversion circuit at the before stage of TC90101FG. In this mode CVBS must be inputted to CVBIN for sync processing, noise dtection and VBI data slice.
TC90101FG
2.2 Input signal amplitude TC90101FG has a 10bit ADC for CVBS & Y signal and 2ch 8bit ADC for C & Cb/Cr. The Dynamic range of ADC is desgned as AVDD *0.4 (Normally 1Vpp at AVDD = 2.5V). The recomemdation amplitude of the input signal : 0.7Vpp at 140IRE (CVBS/Y) . refer to fig-1. * in case of AGC ON, recommendation input signal amplitude is 0.6Vpp (140IRE). (AGC control range is from - 6dB to +3dB.)
Fig-1. Amlitude of CVBS input
Fig-2. Amlitude of C input
Fig-3. Amlitude of base band C signal input
TC90101FG
The amplitude of input signal for 10bit ADC is 0.7Vp-p as 140IRE. in case of C signal for S-video. The amplitude of input signal for C ADC is 0.2Vp-p as 40IRE. (Refer to Fig-2.) The amplitude of input signal for Cb/Cr is 0.7Vp-p as 100% level. (Refer to Fig-3.) (VDD = 2.5V) Input signal vs output signal level Input signal Input signal amplitude Ouput signal level LSB Vp-p CVBS 16-235(pedestal to white 100%) 8bit mode 0.7Vp-p 500mVp-p 16-235(pedestal to white 100%) 8bit mode 0.7Vp-p 500mVp-p C 16-240 8bit mode 0.2Vp-p Burst Cb 0.7Vp-p (100% color) 16-240 8bit mode Cr 0.7Vp-p (100% color) 16-240 8bit mode Input signal amplitude For CVBS and Y, it means 100% level (140IRE). (500mVp-p: pedestal to white 100%.) Cb/Cr, it means 100% color bar Signal. Notice: amplitude of output signal have done by initial value of IIC registers related with gain.
3. Clamping The clam control circuit controls the corect clamping for input signals. TC90101FG has a feed back clamp for H-Sync portion of CVBS/Y input signal to clamp 256LSB(10bit unit). It is selectable to use the 2 types of the feed back clamp (internal circuit or external circuit) via IIC bus. (FBCLMPEX at sub address 03 hex.) In case use external, the clamp signal from YCLAMP1,YCLAMP2(pin 74,75) to be connected with input Terminals. (refer to application circuit.) For C signal, it is biased to 128 LSB. For Cb and Cr signal, it is used keed clamping control to 128 LSB. Input mode CVBS S- Video/ YCbCr CVBS+ YCbCr (1H) Input signal CVBS Y C Cb/Cr CVBS Y Cb/Cr Pin number 81 78 86 88/94 81 78 88/94 ADC
10bit 10bit 8bit 8bit 8bit 10bit 8bit( ) Feed back clamp Keed clamp Sync chip clamp Feed back clamp Keed clamp
Clamping function
Comment
Time constant is selectable for internalClamping mode via BUS FBCLMOD atSub address 32hex. Biased to 128LSB
4. TV system detection for CVBS and S- Video input TC90101FG has 4 types of detection mode and it is selectable via AUTDET at sub address 00hex. AUTODET 00 01 10 Mode
Manual setting EU South America
Fsc detection
4.4336MHz 3.57954MHz 3.57954MHz 3.5756MHz 3.5820MHz 4.4336MHz 3.57954MHz 3.5756MHz 3.5820MHz
Commemt
TV system is set via TV0 - TV3 at sub address 00hex. Priority : 4.43MHz PAL NTSC SECAM (it's not available to detect 3.58MHz PAL signal.) Priority : 3.58MHz PAL 3.58MHz NTSC (it's not available to detect 4.43MHz fsc signal.)
11
Full multi
Priority : PAL
NTSC
SECAM
There is not priority for 50Hz/60Hz(Vertical frequency) detection. VD output (pin 70) is controled via VD.DET at sub address 23hex. [00] : free run. [01] : fixed mode when it detects no signal (The frequency of VDOUT is depends on TVM2.) [10] : Fixed Frequency at Manual setting mode. [11] : VDOUT is depends on TVM2 at all of TV system detection mode.
TC90101FG
5. H/V Sync processing TC90101FG has H/V sync separation circuit and regenrates HD/VD pulse. The phase and width of HD/VD pulse are controled via THRHV at sub address 22hex. [0] : 656 format. [1] : Syncronized with input signal. 6. D2 signal (525p/525p component) processing TC90101FG has D1 and D2 detection circuit and Sync processing for D2 signal. D2 signal is converted as 4:2:2 digital signal by internal ADC. (Sampling rate of Y ADC is 27MHz.) ID-1 data slice for 525p is available but It's not available to use picture implrovement function and Noise level detection, (The sliced data of ID-1 can be read via IIC.) 7. T.O.F (Take Off filter) TC90101FG has Take Off filiter which is in front of color decoder. Characteristic of T.O.F is set via TOF at sub address 0C hex. [000] : Off [001] : type 1- [111] : type 7 (Type 1 : BPF.) 8. Y process a) Vertical enhancement : adjustable coring, gain, and non-linear performance b) LTI function The performance of this function is controlled via Iregisters at 04 and 05 hex. f0 : 3.3MHz / 2.2MHz Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : Off / 1/8 / 1/4 / 1/2 c) Sharpness The performance of this function is controlled via Iregisters at 02 and 03 hex. f0 : 4.2MHz / 3.3MHz Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : -1/4 - Off - 1/2
d) Noise canceller The performance of this function is controlled via Iregisters at 04 hex. f0 : 4.2MHz / 3.3MHz ( It uses same register with f0 of sharpness control.) Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : -1/4 - Off - 1/2 e) Contrast Control range : (1/2) - 2.4 f) Brightness it's effective at the periode of picture signal portion. Control range : -128LSB - 128LSB ( 10bit unit) 9. C process a) ACC control : A reference level is set up by register ACC LEVEL. b) Killer control : sensitivity of killer is set via [BUS KILLV] at sub address 37 hex. In case Killer detection, comb filter for Y becomes off. c) HUE control : Hue control is available for CVBS and C signal of NTSC system. Hue bias : 0 --- +45degree Hue range : -45 degree --- +43.6degree d) Sub color gain control Amplitude of Cb and Cr signals are controlled via IIC. Control range is -6dB --- +2.8dB
TC90101FG
e) CTI function f0 is selectable (1.7MHz/ 3.3MHz). Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2IRE). Gain is selectable (OFF/ x1/8 / x1/4 / x1/2). f) Offset control of the period of picture area The DC level of the Cb and Cr signals are controlled via IIC independently. Control range : -8LSB ---- +7LSB (10bit unit) 10. Output format Output format (data format/clock/phase) is controlled via IIC Bus. Y The Pedestal level is 16LSB at 8bit output format and 64LSB at 10bit output format. C The signal level is 128LSB except for picture periode at 8bit output mode. (10bit mode: 512LSB) The output format (656/601) is set via FORMATO (01h,D3) and the Dynamic range is set via OUTBITS(01h D2) Picture periode of Y output can be controlled by CLP (20h,D0). CLP = [1] : the signal of under 16LSB (8bit mode) is sliced at 16LSB. (standard mode.) CLP = [0] : It's available to output the signal of under 16LSB. Normaly it must be set [1].
YOUT [0-9] (note) COUT [0-9] (note) UVFLAG CKOUT (note) HDOUT VDOUT ODDEVEN VBIREADY
10 10 1 1
13.5MHz/27MHz (601/656) 6.75MHz (13.5/2)MH 13.5MHz/27MHz(/54M Hz)
Y/YC Cr 601/656 C /C CLK 13.5MHz Reference timing pulse for Cb/Cr Polarity : Cr = High(Initial value) 864fH/1728fH 625line source 858fH/1716fH 525line source Polarity : Reversal(Initial value) Re-generated HD Re- generated VD Field indication Flag after VBI data slicing
1 1 1 1
H V V
a) 525 /60Hz CVBS input mode
Sync Through Mode
/
FIELD 1
656 656 Mode
/
1
FIELD 1
Field Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656 Field Line 4 EAV Line 1 EAV Line 10 EAV VBI READY High level output from Line 23 SAV to Line 24 EAV
TC90101FG
2nd Field
Sync Through Mode
656 Mode
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656 Field 2 Line 266 EAV Line 264 EAV Line 273 EAV VBI READY High level output from Line 286 SAV to Line 287 EAV
b) 625 /50Hz CVBS input mode 1 , 3rd Field
Sync Through Mode
656 Mode
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656 Field Line 1 EAV Line 624 EAV Line 23 EAV VBI READY High level output from Line 64 SAV to Line 65 EAV
TC90101FG
2nd ,4th Field
Sync Through Mode
/
656
FIELD 2
Mode 656
/
FIELD 2
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656 Field 2 Line 313 EAV Line 311 EAV Line 336 EAV VBI READY High level output from Line 377 SAV to Line 378 EAV
TC90101FG
11. Feature function a) S/N detection (noise level detection) Noise level detection is performed in the vertical blanking period. The result of noise level detection is stored to IIC read register and it is performed at every field. The related write registers are as follows. EN NOISEV S (sub address 1B hex) : Setup of start line for noise detection. EN NOISEV W (sub address 1A hex) : Setup of the numbers of lines for noise detection . EN NOISEH S (sub address 1A hex) : Setup of start position for noise detection at selected line. EN NOISEH W(sub address 1A hex) : Setup of the period for noise detection at selected line.
Reference position
5.3 s EN NOISEH S
EN NOISEH W
b-1) Video ID (ID-1) data slice function for NTSC 525i signal (CVBS/S-video/Component) ID-1 data slicing is performed at line 20 and 283 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. b-2) Video ID (ID-1) data slice function for NTSC 525p signal (Component) ID-1 data slicing is performed at line 41 in the vertical blanking period for NTSC 525p signal. The sliced data is stored to IIC read register and it is performed at every vertical blanking periode. c) CCD data slice function for US area(NTSC 525i signal (CVBS)) CCD data slicing is performed at line 21 and 284 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. CRI detection, start bit detection and sliced data can be read via IIC bus. d) WSS data slice function for EU area (PAL 625i signal (CVBS)) WSS data slicing is performed at line 23 and 336 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. RUN-IN detection, start detection and sliced data can be read via IIC bus. e) Macrovision detection TC90101FG can detect a pseudo sync, AGC pulse and color stripe. The result of Macrovision detection can be read via IIC bus. AGC function TC90101FG has an AGC function for CVBS and Y signal (S-video). The related write registers are as follows. PAGCON (sub address 2B hex) : Setup for PEAK AGC function. PKLIM (sub address 2B hex) : Setup for limit level for PEAK AGC function. SAGCON (sub address 2B hex) : Setup for SYNC AGC function. (Through mode : Both registers (PAGCON & SAGCON) must be set [0]. )
TC90101FG
12. Insertion of IIC read data for output TC90101FG has IIC read data insert mode for ITU-656 out put format. It's also available for ITU-601 mode. These functions are based on ARIB STD-B6. Selection of the line for IIC read data insertion is set via register at sub address 25hex and 26hex . 25H D7 Insertion ON / OFF control for Horisontal blanking periode. 25H D6 Insertion ON / OFF control for Vertical blanking periode. 25H D5 Selection of insertion for ITU-601 mode 25H D4-D0 Line selection of insertion for Horizontal blanking periode. 26H D7-D4 Line selection of insertion for Vertical blanking periode. TC90101FG uses "the 2nd form of ARIB "
ADF uses fixed value. 1) at the 10bit mode 000h 3FFh 3FFh 2) at the 8 bit mode 00h FFh FFh
DID has 4bit control registers 1) For 10bit mode.
D9(MSB) D8 D7(MSB) 0 D[7:0] D6 0 D5 0 D8
26H D3-D0 .
D7 0 D4 0 D6 1 D5 0 D3 DID3 D4 0 D3 DID3 D2 DID2 D2 DID2 D1 0 D1 DID1 D0(LSB) DID0 D0(LSB) 0
2) For 8bit mode. Notice DID[3:2] 00 is not available when use 8bit mode.
SDID SDID has 4bit control registers 27H . 1) For 10bit mode.
D9(MSB) D8 D7(MSB) SDID7 D[7:0] D8 D7 SDID7 D6 SDID6 D5 SDID5 D4 SDID4 D3 SDID3 D2 SDID2 D1 SDID1 D0(LSB) SDID0
2) For 8bit mode.
D6 SDID6 D5 SDID5 D4 SDID4 D3 SDID3 D2 SDID2 D1 0 D0(LSB) 0
Notice
DID[7:2]
0000 00 is not available when use 8bit mode.
DC uses Fixed value. 1) For 10bit mode.
D9(MSB) 0 D7(MSB) 0 D8 1 D6 1 D7 0 D5 0 D6 0 D4 0 D5 1 D3 1 D4 0 D2 0 D3 0 D1 0 D2 0 D0(LSB) 0 D1 0 D0(LSB) 0
2) For 8bit mode.
TC90101FG
I2C Read Bus insertion specification. In case of 1byte Read register (RD[7:0]), it is superposed as below Read register 1 byte.
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
insertion
D7 0 D6 1
1st word.
D5 RD7 D4 RD6 D3 RD5 D2 RD4 D1 0 D0 0 D(-1) D(-2) 0,0 (10bit mode)
insertion
2nd word
D7 0 D6 0 D5 RD3 D4 RD2 D3 RD1 D2 RD0 D1 1 D0 0 D(-1) D(-2) 0,0 (10bit mode)
Check sum means total value of
to
as below.
10bit mode It calculates total value of the 9bits low ranks of DID, SDID, DC and all of UDW. MSB(D9) means D8 of calculated valu. (it ignores the over flow.)
D9 D8 D8 D7 D6 D5 D4 D3 D2 D1 D0 Total value of the 9bits low ranks of DID, SDID, DC and all of UDW. (it ignores the over flow.)
mode It calculates total value of the 7bits low ranks of DID, SDID, DC and all of UDW. MSB(D7) means D6 of calculated valu. (it ignores the over flow.)
D7 D6 D6 D5 D4 D3 D2 D1 D0 Total value of the 9bits low ranks of DID, SDID, DC and all of UDW.(it ignores the over flow.)
TC90101FG
4. IIC BUS
TC90101FG has two slave address (B2 hexand B0hex). A slave address is chosen by BUSSEL Terminal which is pin 24. (BUSSEL=L B0hex , BUSSEL=H B2hex
R/ W
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
0
0
X
X
Data transmission format
S Slave Address 7bit MSB MSB 0A Sub Address 8bit MSB A Data 8bit AP S: Start condition P: Stop condition A: Acknowledgement
(1) Start condition, Stop condition
(2) Bit transmission
SDA
SDA
SCL
S Start conditions
P Stop conditions
SCL SDA is not changed. SDA is changed.
(3) Acknowledgement
SDA from Master High impedance High impedance
SCL from Master
S Start conditions
1
8
9
TC90101FG
* : Every blank register must be set "0".
TC90101FG
* : Every blank register must be set "0".
TC90101FG
* : Every blank register must be set "0".
TC90101FG
* : Every blank register must be set "0".
TC90101FG
TC90101FG
"
"
"
"
""
TC90101FG
TC90101FG
TC90101FG SECAM Trap Frequency Response
TC90101FG
TC90101FG
"
"
TC90101FG
""
TC90101FG
"
"
TC90101FG
TC90101FG
""
TC90101FG
MAXIMUN RATINGS Vss=0V, Ta=25 Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating.
Operation conditions Vss=0V
TC90101FG
The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling
(1)Power Supply rising These contents are the important items which influence the reliability guarantee of the IC. It is necessary to satisfy the following condition.
(1) P ow er rising condition 3.3V (pow er range : 3.0 m ore than 3.0V 3.6V )
*note1 V D D =3.3V m ore than 0.4V
2.5V (pow er range : 2.3 m ore than 2.3V
2.7V )
*note1 V D D =2.5V m ore than 0.4V 1.5V (pow er range : 1.4 *note1 V D D =1.5V m ore than 0.4V It needs to rise less than 40m s from starting to rise the pow er of 2.5V . (reset release) Term inal 30 RESET A fter all pow ers rising, it is necessary to keep resetting m ore than 0.5m s. A nd it m ust not keep the reset conditions m ore than one m inute. IIC -B us IN Term inal31 S D A Term inal 32 S C L A fter reset release, it is necessary to be m ore than 100ns for IIC B U S control starting. m ore than 1.4V 1.65V )
*note1 S uch the pow er term inal are em bedded the protective diode . It m ust not send a penetration electric current. C ondition: P ow er level of 3.3V line P ow er level of 2.5V line P ow er level of 1.5V line W hen the pow er level of 1.5V line is m ore than 0.4V , 3.3V line and 2.5V line m ust reach the level of pow er m ore than 0.4V . A nd w hen the pow er level of 2.5V line is m ore than 0.4V, 3.3V line m ust reach the level of pow er m ore than 0.4V .
3.3V pow er term inal
2.5V pow er term inal
1.5V pow er term inal
(2) P ow er falling condition It is necessary to fall the pow er of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the pow er of 2.5V line before 3.3V line is fallen. It m ust not send a penetration electric current too .
TC90101FG
ELECTRICAL CHARACTERRISTICS
CHARACTERRISTICS
Notice :
TC90101FG
CHARACTERRISTICS
CHARACTERRISTICS
TC90101FG
Application
Analog GND Digital GND
TC90101FG
PACKAGE OUTLINE LQFP100-P-1414-0.50C UNIT:mm
Weight 0.65g
center
TC90101FG
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
030619EBA
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.

▲Up To Search▲

Price & Availability of TC90101FG

	To Download TC90101FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .